Comments:
Another fairly complex commission for Popular Mechanics Magazine. Total time for
completion was 7 days with various versions completed. The arrangements shown are
not the same ones printed in the magazine.
Description
DDR2 SDRAM or double-data-rate two synchronous dynamic random access memory is a
random access memory technology used for high speed storage of the working data of
a computer or other digital electronic device. It is a part of the SDRAM (synchronous
dynamic random access memory) family of technologies, which is one of many DRAM (dynamic
random access memory) implementations, and is an evolutionary improvement over its
predecessor, DDR SDRAM.
Its primary benefit is the ability to operate the external data bus twice as fast
as DDR SDRAM. This is achieved by improved bus signaling, and by operating the memory
cells at half the clock rate (one quarter of the data transfer rate), rather than
at the clock rate as in the original DDR. DDR2 memory at the same clock speed as
DDR will provide the same bandwidth but markedly higher latency, providing worse
performance.
Overview
Like all SDRAM implementations, DDR2 stores memory in memory cells that are activated
with the use of a clock signal to synchronize their operation with an external data
bus. Like DDR before it, DDR2 cells transfer data both on the rising and falling
edge of the clock (a technique called "dual pumping"). The key difference between
DDR and DDR2 is that in DDR2 the bus is clocked at twice the speed of the memory
cells, so four bits of data can be transferred per memory cell cycle. Thus, without
speeding up the memory cells themselves, DDR2 can effectively operate at twice the
bus speed of DDR.
DDR2's bus frequency is boosted by electrical interface improvements, on-die termination,
prefetch buffers and off-chip drivers. However, latency is greatly increased as a
trade-off. The DDR2 prefetch buffer is 4 bits deep, whereas it is 2 bits deep for
DDR and 8 bits deep for DDR3. While DDR SDRAM has typical read latencies of between
2 and 3 bus cycles, DDR2 may have read latencies between 4 and 6 cycles. Thus, DDR2
memory must be operated at twice the bus speed to achieve the same latency.
Another cost of the increased speed is the requirement that the chips are packaged
in a more expensive and more difficult to assemble BGA package as compared to the
TSSOP package of the previous memory generations such as DDR SDRAM and SDR SDRAM.
This packaging change was necessary to maintain signal integrity at higher speeds.
Power savings are achieved primarily due to an improved manufacturing process through
die shrinkage, resulting in a drop in operating voltage (1.8 V compared to DDR's
2.5 V). The lower memory clock frequency may also enable power reductions in applications
that do not require the highest available speed.
